A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination
A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18um CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.
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Ghanaatian Jahromi, R., Whatmough, P., Constantin, J. H.-F., Teman, A. S., & Burg, A. P. (2016). A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination. 2016 Ieee International Symposium on Circuits and Systems (Iscas), IEEE International Symposium on Circuits and Systems, 2667–2670. https://doi.org/10.1109/ISCAS.2016.7539142
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WOS:000390094702206
2016
New York
978-1-4799-5341-7
4
IEEE International Symposium on Circuits and Systems
2667
2670
REVIEWED
EPFL
| Event name | Event place | Event date |
Montreal, Canada | May 22-25, 2016 | |