Rapid Design Space visualisation through hardware/software partitioning
This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before investing in a particular hardware/ software codesign. 3SP uses a novel program execution model to integrate comprehensive hardware characteristics including clock speed, number of execution units, issue rates, bandwidths and latencies with software program execution, parallelism, control and data flow measurements to estimate codesign performance for evaluating opportunities for hardware acceleration.
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Spacey, S. A., Luk, W., Kelly, P. H. J., & Kuhn, D. (2009). Rapid Design Space visualisation through hardware/software partitioning. 2009 5th Southern Conference on Programmable Logic (SPL), 159–164. https://doi.org/10.1109/SPL.2009.4914913
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2009
978-1-4244-3847-1
159
164
NON-REVIEWED
OTHER
| Event name | Event place | Event date |
São Carlos, Brazil | 1-3 04 2009 | |