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  4. Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic
 
research article

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic

Najmzadeh, M.  
•
Tsuchiya, Y.
•
Bouvet, D.  
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2013
Microelectronic Engineering

In this paper, we report formation of GAA buckled dual Si nanowire MOSFETs including two sub-80 nm Si cores on bulk Si using 0.8 mu m optical lithography and local oxidation for the first time. 0.833 GPa uniaxial tensile stress is measured in the buckled suspended dual Si nanowires using micro-Raman spectroscopy. The array of GAA buckled dual Si nanowire MOSFETs at V-DS = 50 mV shows 64 mV/dec. subthreshold slope and 61% stress-based low-field electron mobility enhancement in comparison to the omega-gate relaxed reference device. Finally, digital logic implementation is demonstrated using multi-gate nanowires on bulk Si. (C) 2013 Elsevier B.V. All rights reserved.

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Type
research article
DOI
10.1016/j.mee.2013.02.003
Web of Science ID

WOS:000326003600055

Author(s)
Najmzadeh, M.  
Tsuchiya, Y.
Bouvet, D.  
Grabinski, W.
Ionescu, A. M.  
Date Issued

2013

Publisher

Elsevier Science Bv

Published in
Microelectronic Engineering
Volume

110

Start page

278

End page

281

Subjects

Multi-gate

•

Si nanowire

•

Local oxidation

•

Strained Si

•

Micro-Raman spectroscopy

•

Transport enhancement

•

Logic

Editorial or Peer reviewed

REVIEWED

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Available on Infoscience
December 9, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/97749
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