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  4. Memory chip or memory array for wide-voltage range in-memory computing using bitline technology
 
patent

Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

Simon, William Andrew  
•
Rios, Marco Antonio  
•
Levisse, Alexandre Sébastien  
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2021

A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.

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Type
patent
EPO Family ID

77274023

Author(s)
Simon, William Andrew  
Rios, Marco Antonio  
Levisse, Alexandre Sébastien  
Zapater, Marina  
Atienza Alonso, David  
TTO classification

TTO:6.2092.1

TTO:6.2092.2

EPFL units
AVP-R-TTO  
ESL  
IdentifierCountry codeKind codeDate issued

US11094355

US

B1

2021-08-17

Available on Infoscience
September 1, 2021
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/181089
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