A 17ps Time-to-digital Converter Implemented in 65nm FPGA Technology

conference paper

A 17ps Time-to-digital Converter Implemented in 65nm FPGA Technology

•

2009

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Name

isfpga09-cfavi.pdf

Access type

openaccess

Size

164.66 KB

Format

Adobe PDF

Checksum (MD5)

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