A 90.6 pJ/pixel 1280×800 65 fps cm-Scale Fully Integrated Video Encoder System Utilizing a 2×2 Microlens Array
This work presents a compact (31.5×10.7×4mm3) video encoder system with a commercial imager, flash, a custom 2×2 microlens array, and an image signal processing (ISP) chip using novel 2×2 intra-frame compression. Leveraging the subframe redundancies inherent to the microlens array, the system achieves >59× compression with >32dB PSNR. With this, the ISP chip fabricated in 28nm CMOS attains 90.6 pJ/pixel energy efficiency at 1280×800, 65fps video stream.
Cite this item
Yang, H., Abillama, P., Wei, X., Huluvallay, M. A. A., Zhang, Q., Chen, J., Yi, J., Chen, C.-S., Bejarano-Carbo, A., Stankovich, M. A., Lentz, M., Bellouard, Y., Stockton, P., Friel, J., Trickey-Glassman, A., Blaauw, D., Sylvester, D., & Kim, H.-S. (2026). A 90.6 pJ/pixel 1280×800 65 fps cm-Scale Fully Integrated Video Encoder System Utilizing a 2×2 Microlens Array. 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 1–3. https://doi.org/10.1109/vlsitechnologyandcir65830.2026.11577285
Click Copy to copy the citation, or select the text manually.
2026-06-14
9798331580964
1
3
REVIEWED
EPFL
| Event name | Event acronym | Event place | Event date |
Honolulu, HI, USA | 2026-06-14 - 2026-06-18 | ||