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  4. Silicon Efficiency in Post-Moore Servers
 
conference paper not in proceedings

Silicon Efficiency in Post-Moore Servers

Ansari, Ali  
•
Lin, Shanqing  
•
Chakraborty, Ayan
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April 28, 2024
Workshop on Hot Topics in Ethical Computer Systems

Server CPUs in the cloud have inherited their core microarchitecture from the desktop and mobile world, with performance primarily measured by single-core IPC. Furthermore, cores are integrated with large cache hierarchies within sockets and rely heavily on these caches to contain chip power envelopes, with little consideration given to utilization by workloads. Wasted silicon impacts both operational and embodied emissions in server platforms. In this work, we measure and compare silicon efficiency measured in performance per area and performance per watt of online and analytic services running on two x86 and an ARM server. We show that while x86 platforms offer higher single-core performance, the ARM server has the potential to achieve up to 2.5× higher socket-level performance per area and performance per watt than the x86 servers in the absence of system-level bottlenecks (e.g., memory or network bandwidth).

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HotEthics_24_Silicon_Efficiency.pdf

Type

Main Document

Version

http://purl.org/coar/version/c_970fb48d4fbd8a85

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openaccess

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N/A

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160.02 KB

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Adobe PDF

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e77ae34ee1257bcea3f11774c65f5174

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