Hardware Decoders for Polar Codes: An Overview
Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders implementing the successive-cancellation, belief propagation, and list decoding algorithms, illustrating their advantages.
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Giard, P., Sarkis, G., Balatsoukas-Stinning, A., Fan, Y., Tsui, C.-Y., Burg, A., Thibeault, C., & Gross, W. J. (2016). Hardware Decoders for Polar Codes: An Overview. 2016 Ieee International Symposium on Circuits and Systems (Iscas), IEEE International Symposium on Circuits and Systems, 149–152. https://doi.org/10.1109/ISCAS.2016.7527192
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WOS:000390094700038
2016
New York
978-1-4799-5341-7
4
IEEE International Symposium on Circuits and Systems
149
152
REVIEWED
EPFL
| Event name | Event place | Event date |
Montreal, CANADA | MAY 22-25, 2016 | |