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  4. On-chip transient stability simulator, 10<sup>4</sup> times faster than real time
 
conference paper

On-chip transient stability simulator, 104 times faster than real time

Fried, R.
•
Cherkaoui, R. S.  
•
Enz, C. C.  
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1997
ICDS'97. Second International Conference on Digital Power System Simulators
Int. Conf. on Digital Power System Simulators (ICDS'97)

This paper suggests several approaches for determining the transient stability of a power network by using an analog VLSI chip for simulating the system behavior. The main advantages of using this method are the much shorter computation time and lower complexity compared to the existing methods that are based on numerical calculations or discrete analog emulators

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Type
conference paper
Web of Science ID

WOS:000084224600012

Author(s)
Fried, R.
Cherkaoui, R. S.  
Enz, C. C.  
Germond, A.  
Vittoz, E. A.  
Date Issued

1997

Published in
ICDS'97. Second International Conference on Digital Power System Simulators
ISBN of the book

1-56612-062-4

Start page

79

End page

84

Subjects

analogue integrated circuits

•

analogue processing circuits

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analogue simulation

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power system analysis computing

•

power system stability

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power system transients

•

VLSI

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on-chip transient stability simulator

•

power network model

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analog VLSI chip

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system behavior simulation

•

analog VLSI architectures

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DC simulation

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two-machine system

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on-chip analog simulation

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LRE  
LSI2  
SCI-STI-FR  
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Event nameEvent placeEvent date
Int. Conf. on Digital Power System Simulators (ICDS'97)

Montreal

28-30 may 1997

Available on Infoscience
April 4, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/4435
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