Global modeling strategy of parasitic coupled currents induced by minority-carrier propagation in semiconductor substrates
This paper presents a modeling strategy to simulate the propagation of electrical perturbations induced by direct biasing of substrate junctions. Usually, this is done by identifying parasitic substrate devices such as bipolar transistors. However, mapping a topology with these bipolar transistors rapidly reaches its limits when several junctions are acting at the same time. In this paper, we propose a new modeling methodology of parasitic signals. It relies on a generalized model of p-n junctions and resistances that takes into account minority-carrier densities and gradients at the boundaries. We show that bipolar-transistor- and thyristor-related effects can be obtained from a network interconnection of these extended devices. Furthermore, we show that this modeling approach could be easily extended to simulate complex 3-D layouts. © 2009 IEEE.
WOS:000273088600032
2-s2.0-73349135917
2010
57
1
263
272
Ecole Polytechnique Fédérale de Lausanne, 1015 Laussane, Switzerland
Export Date: 19 January 2010
Source: Scopus
Art. No.: 5339188
References: Murari, B., Bertotti, F., Vignola, G., (2002) Smart Power ICs, pp. 218-220. , 2nd ed. Berlin, Germany: Springer-Verlag; Clement, F.J.R., Zysman, E., Kayal, M., Declercq, M., LAYIN: Toward a global solution for parasitic coupling modeling and visualization (1994) Proc. IEEE Custom Integr. Circuits Conf., pp. 537-540; Birrer, P., Fiez, T.S., Mayaram, K., Silencer!: A tool for substrate noise coupling analysis (2004) Proc. IEEE SOC Conf., pp. 105-108; (2009) Coupling Wave Solutions (CWS), , http://www.cwseda.com/, accessed January. [Online]. Available; Schenkel, M., (2003) Substrate Current Effects in Smart Power ICs, , Konstanz, Germany: Hartung-Gorre-Verlag; Casalta, J.M., Aragons, X., Rubio, A., Substrate coupling evaluation in BiCMOS technology (1997) IEEE J. Solid-State Circuits, 32 (4), pp. 568-603. , Apr; Kayal, M., Saez, R.L., Pastre, M., The reduction of switching noise using CMOS current steering logic (2003) Substrate Noise Coupling in Mixed-Signal ASICs, pp. 223-228. , Norwell, MA: Kluwer; Oehmen, J., Olbrich, M., Hedrich, L., Barke, E., Modeling lateral parasitic transistors in smart power ICs (2006) IEEE Trans. Device Mater. Rel., 6 (3), pp. 408-420. , Sep; Lo Conte, F., Pastre, M., Sallese, J.M., Krummenacher, F., Kayal, M., Substrate current modeling for high-voltage smart power BCD technology (2008) IEEE NEWCAST-TAISA, pp. 141-144. , Jun; Neamen, D.A., (1992) Semiconductor Physics and Devices, , Homewood IL: Irwin; Sze, S.M., (1981) Physics of Semiconductor Device, , 2nd ed. Hoboken, NJ: Wiley; (2009) Cadence Virtuoso Multi-Mode Simulation, , http://www.cadence.com/rl/Resources/datasheets/virtuoso-mmsim.pdf, accessed on Jan. [Online]. Available; (2009) Sentaurus Device Datasheet, , http://www.synopsys.com/Tools/TCAD/CapsuleModule/sdevice-ds.pdf, accessed on Jan. [Online]. Available; Gray, P.R., Meyer, R.G., (1977) Analysis and Design of Analog Integrated Circuits, , Hoboken, NJ: Wiley
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