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  4. 3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devices
 
conference paper

3D Nanostructured Silicon Relying on Hard Mask Engineering for High Temperature Annealing (HME-HTA) Processes for Electronic Devices

Bopp, M.  
•
Coronel, P.
•
Judong, F.
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2008
NSTI Nanotech, The Nanotechnology Conference and Trade Show, 2008

Annealing silicon at high temperatures in hydrogen ambiance has been reported to induce surface diffusion of silicon; in these conditions, adapted 2D arrays of trenches etched in Bulk Si are transformed into buried cavities creating suspended membranes. A 3D nanostructuration of silicon through hard mask engineering and high temperature annealing in hydrogen ambiance is reported. By using a nitride-oxide hard mask stack instead of a sacrificial oxide hard mask for a free surface (maskless) annealing, we open new technological and design possibilities using 2D arrays of various geometry trenches. Implications and potential device applications are discussed.

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Type
conference paper
Author(s)
Bopp, M.  
Coronel, P.
Judong, F.
Jouannic, K.
Talbot, A.
Ristoiu, D.
Pribat, C.
Bardos, N.
Pico, F.
Samson, M. P.
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Date Issued

2008

Published in
NSTI Nanotech, The Nanotechnology Conference and Trade Show, 2008
Subjects

silicon high temperature annealing

•

hard mask

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buried cavity

•

Independant double gate transistor

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Available on Infoscience
July 15, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/41322
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