A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Roth, C.; Meinerzhagen, Pascal Andreas; Studer, C.; Burg, Andreas Peter

doi:10.1109/ASSCC.2010.5716618

conference paper

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

Roth, C.

•

Meinerzhagen, Pascal Andreas

•

Studer, C.

2010

2010 IEEE Asian Solid-State Circuits Conference

2010 IEEE Asian Solid-State Circuits Conference (A-SSCC)

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11n). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90nm CMOS ASIC has a core area of 1.77mm2 and achieves a maximum throughput of 680 Mbps at 346MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8 pJ/bit/iteration at a nominal operating voltage of 1.0V.

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Roth, C., Meinerzhagen, P. A., Studer, C., & Burg, A. P. (2010). A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS. 2010 IEEE Asian Solid-State Circuits Conference, 1–4. https://doi.org/10.1109/ASSCC.2010.5716618

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