conference paper
Evaluation of the SPUR Lisp Architecture
1986
13th International Symposium on Computer Architecture
The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle time SPUR will run Common Lisp programs at least as fast as a Symbolies 3600 or a DEC VAX 8600. This paper explains SPUR's instruction set architecture and provides measurements of how certain components of the architecture perform.
Type
conference paper
Author(s)
Taylor, George S.
Hilfinger, Paul N.
Larus, James R.
Patterson, David A.
Zorn, Benjamin G.
Date Issued
1986
Publisher
Published in
13th International Symposium on Computer Architecture
Start page
444
End page
452
Editorial or Peer reviewed
REVIEWED
Written at
OTHER
EPFL units
Available on Infoscience
December 23, 2013
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