Modern society is dependent on reliable electricity for security, health, communication, transportation, finance, computers and nearly all aspects of the contemporary life. Providing reliable electricity is a very complex challenge. It involves real-time metering, real-time assessment, control and coordination of hundreds of production centers. Power consumption is steadily increasing and the power system is always operating closer to its limits. Introduction to smart-grid provides more and more data to be collected for the operation center by means of smart-metering for a better knowledge of the system. Moreover, focus is put on decentralized and stochastic green energy sources, leading to a much more complex and less predictable power system. Guarantying security of supply with these new requirements involves further enhancement for faster power system simulators. Indeed, they can provide online security assessment for better real-time control. Time-domain simulations are probably the most demanding in term of computation power. Existing time-domain simulators are based on time-consuming algorithm and targets very precise results. An effective way to accelerate the computational speed of power system assessment simulators is to use analog or mixed-signal emulation. Instead computing numerical matrix calculations of the grid this technique is based on a quasi-instantaneous analog Kirchhoff solver. It provides an intrinsic parallel computer and simulation time is independent of the analyzed power system topology size. This work addresses the development of a new power system emulation approach based on mixed-signal dedicated electronics hardware. Mixed-signal or hybrid electronics uses the coexistence of both digital and analog implementation. The digital functions are intended to facilitate the model portability when analog functions are used for achieving parallelism and speed enhancement. This thesis covers theoretical principles to the realization of a first power system emulation-on-chip (PSEoC) by means of application specific integrated circuit (ASIC). Moreover, different hardware platform (HDP) have been designed, realized and tested for demonstrating the performances by measurement. Within the framework of this work, we restrict our developments to transient stability and cover applications such N-1 contingency analysis and Critical Clearing Time (CCT) analysis. The approach used is called the phasor emulation (PE) approach. It is based on a mathematical abstraction of the grid where the transmission lines are represented by multiple programmable resistive networks, connected in array with CMOS analog switches. Generators and loads model are then computed through current-techniques blocks, embedded processors or FPGAs. Four HDP are presented: - The first electronics implementation provides a quasi-full analog computer and illustrates the limitations in terms of accuracy of such implementation without calibration. - The second uses multiple embedded 32-bit processors with analog emulation of the grid. It illustrates a comparison in term of accuracy between standard electronic and ASIC implementations (0.35um 3.3V CMOS technology) for a 16 node reconfigurable power system topology. - The third uses multiple FPGA processing units with analog emulation of the grid. It covers applications such N-1 contingency analysis and Critical Clearing Time (CCT) analysis for a 96 nodes reconfigurable power system topology. - Finally, the forth is based on PSEoC and the design of a dedicated ASICs developed for time-domain power system emulation. Main enhancement of this development is the design and realization of hybrid R-A/D C-A/D converter in 0.35um 3.3V CMOS technology. The emulated phenomena are shown to be between 100 to 1000 time faster than the real-time phenomena proving the high-speed capabilities of mixed-signal emulation approach.