Ordered statistics decoding (OSD) is a universal decoding algorithm for short-length linear block codes that approaches maximum likelihood decoding when run at sufficiently high order. However, the high computational complexity and latency of Gaussian elimination make it challenging for OSD implementations to meet stringent latency constraints. In this paper, we design a hardware decoder for OSD with order one, featuring an unfolded Gaussian elimination architecture with configurable parallelism. The proposed architecture can efficiently process multiple matrix columns and guarantees a low decoding latency. Based on 65 nm CMOS technology, the synthesis results show a worst-case throughput of 958 Mbps for a (128, 105) polar code at a frequency of 575 MHz.