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Raghav, S., Ruggiero, M., Atienza Alonso, D., Pinto, C., Marongio, A., & Benini, L. (2010). Scalable instruction set simulator for thousand-core architectures running on GPGPUs. Proceedings of the IEEE 2010 International Conference on High Performance Computing and Simulation (HPCS 2010), 1(1), 459–466. https://doi.org/10.1109/HPCS.2010.5547092

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