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  4. A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS
 
research article

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

Uran, Arda  
•
Türe, Kerim  
•
Aprile, Cosimo  
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2022
IEEE Journal of Solid-State Circuits

Next generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this paper presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. An energy-area efficient 10-bit 20 kS/s front-end amplifies and digitizes the neural signals within the LFP and AP bands. The raw data from each channel is decomposed into spectral features using a Compressed Hadamard Transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm, such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and offline experiments. The prototype fabricated in 65nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overallsignal chain consumes 2.6 μW and occupies 0.021 mm2 per channel, pointing towards its feasibility for thousand-channel single-die neural recording systems.

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JSSC3161296[1].pdf

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Postprint

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http://purl.org/coar/version/c_ab4af688f83e57aa

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openaccess

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copyright

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5.93 MB

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Adobe PDF

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ad40c46ce409470984b8fc3edd479c3f

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