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research article

Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture

Mahapatra, S.  
•
Ionescu, A. M.  
2005
IEEE Transactions on Nanotechnology
  • Details
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Type
research article
DOI
10.1109/TNANO.2005.858602
Web of Science ID

WOS:000233341100009

Author(s)
Mahapatra, S.  
Ionescu, A. M.  
Date Issued

2005

Published in
IEEE Transactions on Nanotechnology
Volume

4

Issue

6

Start page

705

End page

714

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Available on Infoscience
May 16, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/6954
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