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research article

High aspect ratio sub-micron trenches on silicon-on-insulator and bulk silicon

Hermersdorf, M.
•
Hibert, C.  
•
Grogg, D.
Show more
2011
Microelectronic Engineering

This paper reports on the fabrication of sub-micron trenches on silicon-on-insulator (SOI) required in many MEMS devices and on bulk silicon. Trenches in the range of 100-500 nm had been etched with the deep reactive ion etching (DRIE) by using the SHARP (super high aspect ratio process) [1] optimized Bosch process with low frequency (LF) biased substrate. For comparison, the same trenches were etched with reactive ion etching (RIE) based on chlorine chemistry and with the radio frequency (RF) biased substrate DRIE SHARP optimized Bosch process. The comparison clearly illustrates the superiority of the LF biased substrate Bosch process. Aspect ratios of over 20 were achieved with nearly 90 angled and smooth sidewalls. It was found out that the scalloping effect got reduced by decreasing trench width. 200 nm and 150 nm comb-trenches with 200 nm and 150 nm spacing respectively and with an aspect ratio of over 20 were fabricated to demonstrate the controllability and repeatability of the trenches fabrication. (C) 2011 Elsevier B.V. All rights reserved.

  • Details
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Type
research article
DOI
10.1016/j.mee.2011.02.030
Web of Science ID

WOS:000293663400231

Author(s)
Hermersdorf, M.
Hibert, C.  
Grogg, D.
Ionescu, A. M.  
Date Issued

2011

Published in
Microelectronic Engineering
Volume

88

Start page

2556

End page

2558

Subjects

Soi

•

Drie

•

High aspect ratio

•

Sub-micron trenches

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
CMI  
NANOLAB  
Available on Infoscience
December 16, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/73622
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