Design Trade-offs of Second Harmonic Minimization in Solid-State Transformers
In two-stage solid-state transformers (SSTs) equipped with LLC DC/DC converters for galvanic isolation, fixed-frequency open-loop operation of LLC stages has been a straightforward and prevailing design choice. Meanwhile, with a closed-loop-operated LLC converter, the propagation of second-order harmonics can be avoided to the output, and therefore, this would address the harmonic issue of single-phase AC/DC conversion without selecting bulky DC-link capacitors that negatively affect the system's volume, weight, and cost. Yet, for this solution to be influential in capacitance reduction, there is an LLC converter design issue other than the closed-loop implementation since the gain characteristics of the LLC stage should allow notable ripple voltage minimization, which is in contrast with its nature. In this paper, accordingly, an LLC parameter design strategy is presented to optimize the gain characteristic of the LLC resonant network, considering the required gain for defined ripple voltages while maintaining soft-switching and the proper performance of the converter. Moreover, the paper explores efficiency and power density trade-offs between the capacitor sizing and LLC DC/DC converter stage design of SST for the closed-loop operation by linking these benchmarks and harmonic mitigation capacity to only LLC's peak magnetizing current. Thereby, the most fitting LLC parameters are presented to allow optimum second-harmonic minimization capability and, thus, DC-link capacitance reduction for the SST. Afterward, the impact of the proposed LLC parameters is analyzed on the MFT design of the LLC converter, and various design choices are provided based on optimization goals, such as the overall efficiency, volumetric and gravimetric power density. The effectiveness of the proposed approaches is validated by simulation and experimental test results.
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