Cryogenic CMOS-SPAD and Digital SiPM Architectures for Neutrino Detection and Single-Photon Sensing Applications
High-performance single-photon detection has become critical for applications ranging from autonomous navigation and non-invasive biomedical diagnostics to large-scale fundamental physics experiments. Complementary metal-oxide-semiconductor single-photon avalanche diodes (CMOS-SPADs) meet this demand by combining single-photon sensitivity with the integration density and low cost of standard CMOS processes. However, achieving high photon detection probability (PDP), low dark count rate (DCR), and precise timing resolution in advanced nodes requires co-optimization of the device structure and the dielectric stack. Moreover, SPAD behavior at deep-cryogenic temperatures, as required by the Deep Underground Neutrino Experiment (DUNE), remains poorly characterized.
This thesis presents a progression of time-resolved SPAD technology, from device engineering and integrated circuit (IC) design to system-level validation. First, structural innovations are implemented in 55 nm BCDlite and 22 nm fully-depleted silicon-on-insulator (FDSOI) technologies. These include a canyon-etching strategy for back-end-of-line (BEOL) dielectric optimization and selective buried oxide (BOX) etching to form vertical junctions in FDSOI. Second, to overcome cryogenic afterpulsing, a fast-readout IC with active quenching and programmable hold-off is developed. A scalable digital silicon photomultiplier (DSiPM) with autonomous self-recharging is derived from it. Third, a dual-purpose 512-SPAD IC integrating a hierarchical time-to-digital converter (TDC) is designed for simultaneous light detection and ranging (LiDAR) and photon intensity mapping. Finally, a commercial 512 Ã 512 SPAD array is deployed in a custom optical setup for time-gated, non-invasive Raman spectroscopy targeting glucose detection.
At the device level, a canyon-etched front-side illuminated (FSI) SPAD in 55 nm BCDlite achieves a record peak PDP of 89.4% at 450 nm, the highest reported among FSI SPADs. It also has a normalized average DCR of 38.2 cps/µm² at room temperature and a timing jitter of 66 ps FWHM at an excess bias of 7 V. At the IC level, the active hold-off circuit enables reliable single-photon counting at 85 K by enforcing a 4 µs dead time that fully suppresses afterpulsing. Arrhenius analysis confirms that the underlying mechanism is thermally activated trap release. The LiDAR IC achieves a 10 ps arrival-time resolution using a winner-take-all (WTA) decision-tree front-end and a coarse-fine TDC. At the system level, the time-gated Raman setup isolates the characteristic glucose peaks at 1064 cm⠻¹ and 1125 cm⠻¹ from strong fluorescence backgrounds through incremental 54 ps gate shifting.
By bridging device optimization, custom IC design, and system-level optical applications, this thesis establishes a scalable and robust foundation for next-generation single-photon sensing in physics, biomedical diagnostics, and autonomous navigation.
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Ha, W. Y. (2026). Cryogenic CMOS-SPAD and Digital SiPM Architectures for Neutrino Detection and Single-Photon Sensing Applications (Publication No. 11829) [PhD thesis, École Polytechnique Fédérale de Lausanne; Supervised by E. Charbon]. https://doi.org/10.5075/epfl-thesis-11829
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