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  4. 3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems
 
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conference paper

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

Cuesta, David
•
Risco, Jose L.
•
Ayala Rodrigo, José Luis
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2011
Proceedings of the 12th IEEE Latin-American Test Workshop (LATW11)
12th IEEE Latin-American Test Workshop (LATW11)

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in the optimization approach; (2) an efficient Mixed Integer Linear Programming (MILP) representation of the floorplanning model; and (3) a smooth integration of the MILP model with an accurate thermal modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel’s SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system.

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LATW2011-cuesta_et_al.pdf

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