Monolithic pixel sensors integrate the sensor matrix and readout in the same silicon die, and therefore present several advantages over the more largely used hybrid detectors in high-energy physics. They offer an easier detector assembly, lower cost, lower material budget and lower power consumption. This work has been carried out in the EP-R&D program at CERN and its main goal is the development of analog readout solutions for monolithic sensors able to cope with the requirements of future high-energy physics experiments. The optimization of an analog front-end amplifier integrated in a large-scale monolithic sensor targeting the requirements of the outer layer of the ATLAS Inner Tracker upgrade is shown. The chip is manufactured in the TowerJazz 180 nm imaging process. The sensor is designed with a small collection electrode offering therefore a small capacitance (< 5 fF), key feature to achieve high analog performance. Furthermore, it implements a process modification which enhances the charge collection properties of the sensor and its radiation tolerance. The chip has been extensively tested and the characterization results relevant to the front-end circuit are also presented. To cope with the demand of higher granularity and lower material budget of future high-energy physics experiments, the possibility of moving future monolithic developments in a smaller node technology has been explored in the framework of the EP-R&D program. One of the main targeted applications is the ALICE Inner Tracking System upgrade. The 65 nm imaging technology from the Tower Partners Semiconductor Co. was considered as a possible candidate. Several test structures have been therefore developed to validate this technology for HEP applications. Amongst these, an analog test structure allows to monitor the analog behavior of the sensor and its charge collection properties. Another prototype, instead, allows to characterize the sensor with a fully-featured readout, composed of an analog front-end amplifier and discriminator followed by a digital logic. This work presents the design of these structures and discusses their main characterization results. Another important target of the R&D effort is to prove the possibility of realizing wafer-scale monolithic sensors with the stitching technique offered by the aforementioned 65 nm process. Large-scale sensors facilitate the coverage of large sensitive areas and, if able to cover the entire sensitive area of a detector, eliminate the need of tiling multiple chips achieving a significant reduction of the material budget. The upgrade of the ALICE Inner Tracking System is based on this idea. Two wafer-scale sensors have been developed to gain fundamental knowledge and experience on the stitching technique for particle detection. A primary concern in designing such large systems is to obtain a high yield. The two prototypes feature different readout architectures and cope differently with this issue. An overview on the main design aspects of these two structures is given in this manuscript.