A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS
Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. We show how to overcome these effects for the core and memory by exploiting the strong body factor of deeply-depleted channel CMOS at 0.5 V, compensating frequency over PVT to +/- 6%, achieving 30x frequency and 20x leakage scaling in a 2.56 mu W/MHz 32 bit RISC Core with 3.13 nW/kB 2.5 mu W/MHz SRAM. Frequency-leakage configurability in core and SRAM through adaptive body bias at fixed supply voltage is implemented using a novel automatic analog-assisted I-ON-controlled approach.
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Pons, M., Mueller, C. T., Ruffieux, D., Nagel, J.-L., Emery, S., Burg, A., Tanahashi, S., Tanaka, Y., & Takeuchi, A. (2019, January 1). A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS. 2019 Ieee Custom Integrated Circuits Conference (Cicc), IEEE Custom Integrated Circuits Conference. 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX. https://doi.org/10.1109/CICC.2019.8780199
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WOS:000501010700042
2019-01-01
New York
978-1-5386-9395-7
IEEE Custom Integrated Circuits Conference
REVIEWED
EPFL
| Event name | Event place | Event date |
Austin, TX | Apr 14-17, 2019 | |