Ionizing and non-ionizing radiation is known to cause damages in electronic components, resulting in reduced performance and possible failure. This is a major issue for any application where electronics operate in a radioactive environment. An extreme example is the future High Luminosity Large Hadron Collider (HL-LHC) at CERN, where Total Ionizing Doses (TID) of 1 Grad(SiO2) and fluences of 10^16 particles/cm2 will be reached in the inner layers of particle detectors after 10 years of operation.

The radiation levels in question are orders of magnitude higher than those typically encountered in space applications and require a careful and dedicated investigation of radiation effects in the CMOS technologies used in the ASICs designed for particle detectors. This thesis explores several topics related to the qualification of technologies for use in CERN particle detector electronics.

The results of an unprecedented monitoring effort on dozens of chips in the 130-65 nm CMOS technologies used for ASICs develop