Efficient ASIC implementation of a real-time depth mapping stereo vision system
This paper presents a fast and area-efficient implementation of a real-time stereo vision algorithm for spatial depth mapping. The design combines two well-known area-based approaches to stereo thatching and includes an occlusion detection method. Hardware efficiency is achieved by storing only partial images on-chip, avoiding full-sized frame buffers. A low-latency dataflow-oriented structure makes it possible to process 256 x 192 pixel Input streams with a rate In excess of 50 frames per second, amounting to more than 54 million pixel x disparity measurements per second (PDS) (for a 25-pixel disparity range), or roughly 18 GOPS. The design has been Integrated In a 0.25 mu m standard CMOS technology and occupies an area of less than 3 mm(2).
Cite this item
Moser, S., Isler, O., Gurkaynak, F. K., Burg, A., Felber, N., Kaeslin, H., Fichtner, W., & Kuhn, M. (2003). Efficient ASIC implementation of a real-time depth mapping stereo vision system. Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, 1478–1481. https://doi.org/10.1109/MWSCAS.2003.1562575
Click Copy to copy the citation, or select the text manually.
WOS:000234964300360
2003
0-7803-8294-3
1478
1481
REVIEWED
EPFL
| Event name | Event place | Event date |
Cairo, EGYPT | Dec 27-30, 2003 | |