Non volatile flash memories based on nanoparticles are one of the possible routes to further downscaling of CMOS technology. The increase of scale integration should involve some new features for memory cells such as Coulomb blockade and quantized charging effects. These previously mentioned effects appear at room temperature, for nanometer sized nanoparticles (nps), if their number is reduced to a few or even a single particle. Fabrication of 2D arrays of Si nanoparticles have been previously demonstrated using, ultra low energy ion implantation (1keV) into an ultra thin SiO2 layer (7nm), followed by annealing. Nano-MOS capacitors were then elaborated using e-beam lithography, creating gates at the nanometer scale capable of addressing only a few nps and obtaining a single electron transfer sensitivity. However, this complex process has many disadvantages and suffers from non-reproducibility. In this work, we propose an alternative approach combining stencil lithography masks and low energy ion implantation (called “stencil mask ion implantation process”). The process leads to a localized synthesis of only few self-organised nps. In this process, the SiO2 thin layer is irradiated by a 1keV silicon ion beam through a stencil mask, which contains a periodic array of membrane apertures. The size of these apertures are in the 50nm to 2um range and shaped as, square, circle, cross, etc. This stencil mask locally modulates the dose of the implanted Si ions which produces nps in these Si rich regions upon annealing. For the smallest membrane apertures the number of fabricated nps could be reduce to one. After the removal of the stencil and after thermal annealing, the photoluminescence (PL) spectroscopic imaging under a confocal microscope is performed to detect the nps rich areas by using their quantum confinement linked red light emission. The image of the PL intensity is found to perfectly mimic the mask geometry. Moreover, a blueshift of the PL energy is detected near mask edge window which is probably due to the smaller sizes of Si-nps. Energy filtered transmission electron microscopy is underway and is used to determine the density and the size distribution of these nps. Using these few nps of localized 2D-layers samples, elaboration of more robust nano-MOS devices is underway, revealing the nps quantized charging features in a more reliable way. These two kinds of nano-MOS devices will be compared via the I-V and I-t electrical characterization.