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research article

A circuit-level substrate current model for smart-power ICs

Lo Conte, F.  
•
Sallese, Jean-Michel  
•
Pastre, M.  
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2010
IEEE Transactions on Power Electronics

This paper presents a new modeling methodology accounting for generation and propagation of minority carriers that can be used directly in circuit-level simulators in order to estimate coupled parasitic currents. The method is based on a new compact model of basic components (p-n junction and resistance) and takes into account minority carriers at the boundary. An equivalent circuit schematic of the substrate is built by identifying these basic elements in the substrate and interconnecting them. Parasitic effects such as bipolar or latch-up effects result from the continuity of minority carriers guaranteed by the components models. A structure similar to a half-bridge perturbing sensitive n-wells has been simulated. It is composed by four p-n junctions connected together by their common p-doped sides. The results are in good agreement with those obtained from physical device simulations. © 2010 IEEE.

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Type
research article
DOI
10.1109/TPEL.2010.2048761
Web of Science ID

WOS:000283991700021

Author(s)
Lo Conte, F.  
Sallese, Jean-Michel  
Pastre, M.  
Krummenacher, F.  
Kayal, M.  
Date Issued

2010

Publisher

Institute of Electrical and Electronics Engineers

Published in
IEEE Transactions on Power Electronics
Volume

25

Issue

9

Start page

2433

End page

2439

Subjects

Smart power IC

•

Integrated circuit

•

Methodology modeling

•

Noise

•

Parasitic coupling

•

Power semiconductor devices

•

Power parasitic modeling

•

Substrate modeling

•

Lumped modeling

Editorial or Peer reviewed

REVIEWED

Written at

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October 12, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/55406
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