A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance
In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV/root Hz. The receiver consists of the reception coil, an on-chip tuning capacitor an LNA and a 50 Omega output buffer. The system is designedfor operation in a B-0-field of 1.5 T corresponding to a frequency of 63MHz. It is implemented in a 0.35 mu m CMOS high voltage process and occupies a chip area of 500 mu m x 760 mu m.
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Anders, J., Reymond, S., Boero, G., & Scheffler, K. (2009). A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance. 13Th International Conference on Biomedical Engineering, Vols 1-3, IFMBE Proceedings; 23, 89–93. https://doi.org/10.1007/978-3-540-92841-6_22
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WOS:000268245600022
2009
978-3-540-92840-9
IFMBE Proceedings; 23
89
93
REVIEWED
EPFL
| Event name | Event place | Event date |
Singapore, SINGAPORE | Dec 03-06, 2008 | |