One of the vital components of Very Large Scale Integration (VLSI) is embedded memories. Embedded memories are widely used in various system-on-chip (SoC) architectures, including communication systems, consumer electronics, and the automotive applications. In fact, the demand for the high-performance, low power, and small area embedded memorieshas even increased dramatically with the recent advent of Artificial Intelligence.

The most commonly used embedded memory in SoC devices is the six-transistor static random-access memory (6T-SRAM). However, 6T-SRAM structures are limited in terms of power and area efficiency. Each bit requires six transistors for storage, and the inherent latch structure consumes significant leakage power. Additionally, 6T-SRAM requires specific sizing ratios to ensure reliable write operations due to its latch-based architecture. These sizing constraints make 6T-SRAM highly sensitive to process variations, further limiting its scalability.

An alternative to SRAM is the embedded gain-cell (GC) RAM, which generally requires only two to four transistors per bit, offering a better area density than 6T-SRAM. GC-RAMs have no direct path to the supply, resulting in lower leakage currents. Although GC-RAM can achieve speeds comparable to SRAM, it suffers from limited data retention times. Systematic refresh operations can mitigate retention time issues in mature process nodes. However, advanced process nodes face even lower retention times, necessitating frequent refresh cycles. These frequent refresh operations increase power consumption and reduce memory availability, presenting a significant challenge for the practical application of GC-RAM arrays. Further research is crucial to enhance data retention times in advanced process nodes, enabling the full utilization of GC-RAM benefits.

This thesis provides a detailed exploration of the GC-RAM memory array design process, from the bitcell level to the macro level, along with innovative assist techniques implemented to maximize data retention time. These memory arrays are optimized to achieve maximized data retention time and high density, without compromising power efficiency or frequency.

In this thesis, three memory arrays are designed and fabricated by using proposed verification method across three different process nodes. The process nodes are 65 nm bulk Complementary Metal-Oxide-Semiconductor (CMOS), 28 nm Fully Depleted Silicon On Insulator (FD-SOI) and 16 nm Fin Field Effect Transistor (FINFET). In each process node, the designed arrays outperform state-of-the-art GC-RAMs in the same technology node and demonstrate substantial area and power advantage over the 6T-SRAM.