Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power dissipation would be lowered significantly if FETs could be operated at lower voltages, which is in contrast with having a sufficiently high on-current. In that pursuit, it was proposed that the minimum voltage requirement could be overcome if the ordinary gate oxide could be replaced by another stack that provides an effective negative capacitance (NC). For a MOSFET, a negative capacitor in the gate stack can make the total capacitance, looking into the gate, larger than the classical MOS capacitance. Thus, to induce the same amount of charge in the channel, one would require a smaller voltage than what would be needed classically. It is well established that ferroelectric materials can provide an effective NC in a certain range of polarization.

The objective of this thesis is to study the negative capacitance effect of ferroelectrics on the performance of field-effect transistors. For this purpose, various NC-FETs and NC-TFETs have been designed and characterized. First, this work proposes a matching condition between the ferroelectric's NC and the gate intrinsic capacitance of the reference transistor to ensure the maximum enhancement due to the NC effect as well as optimizing the hysteretic behavior. Afterward, based on the proposed condition, hysteretic, low hysteresis, and non-hysteretic NC-FETs using 28 nm CMOS node planar MOSFETs and FD-SOI FETs are experimentally demonstrated. In another device structure, the impact of the ferroelectric NC on tunnel FETs is investigated and discussed. It is validated that by combining the advantages of band-to-band tunneling as the carrier injection mechanism and the NC of ferroelectrics, it is possible to obtain steep slope energy efficient switches with improved analog and digital performances. Novel InAs/InGaAsSb/GaSb nanowire TFETs and InGaAs planar TFETs are employed as the reference transistors. The potentials of the recently proposed CMOS compatible ferroelectric, silicon-doped HfO2, as the NC booster is investigated. The results show that further engineering and advancement is required to optimize the leakage and remanent polarization of this type of ferroelectrics. This work also suggests that a ferroelectric TFET using Si:HfO2 can be considered as an energy efficient 1T memory that can be scaled down to sub-100 nm technology nodes. Overall, this Ph.D. work highlights and validates the potentials of ferroelectric field-effect transistors for both steep slope and memory applications.