conference paper
A Low-Power Programmable Dynamic Frequency Divider
2008
Proc. of the European Solid-State Circ. Conf. (ESSCIRC)
In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.
Type
conference paper
Author(s)
Date Issued
2008
Published in
Proc. of the European Solid-State Circ. Conf. (ESSCIRC)
Start page
370
End page
373
Editorial or Peer reviewed
REVIEWED
Written at
EPFL
EPFL units
Available on Infoscience
June 24, 2010
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