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  4. NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs
 
conference paper

NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs

Seiculescu, Ciprian  
•
Murali, Srinivasan  
•
Benini, Luca  
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2009
Proceedings of the Design Automation Conference (DAC 2009)
Design Automation Conference (DAC 2009)

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in allowing the shutdown of the islands. In this paper, we present a synthesis approach to obtain customized application-specific Networks on Chips (NoCs) that can support the shutdown of voltage islands. Our results on realistic SoC benchmarks show that the re- sulting NoC designs only have a negligible overhead in SoC active power consumption (average of 3%) and area (average of 0.5%) to support the shutdown of islands. The shutdown support provided can lead to a significant leakage and hence total power savings.

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Type
conference paper
DOI
10.1145/1629911.1630121
Web of Science ID

WOS:000279394200164

Author(s)
Seiculescu, Ciprian  
Murali, Srinivasan  
Benini, Luca  
De Micheli, Giovanni  
Date Issued

2009

Published in
Proceedings of the Design Automation Conference (DAC 2009)
Start page

822

End page

825

Subjects

NoC

•

voltage islands

•

shutdown

•

leakage power

•

topology

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSI1  
Event nameEvent placeEvent date
Design Automation Conference (DAC 2009)

San Francisco, California, USA

July 26-31, 2009

Available on Infoscience
September 22, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/42778
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