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research article

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

Conte, Fabrizio Lo  
•
Sallese, Jean-Michel  
•
Kayal, Maher  
2011
IEEE Transactions on Power Electronics

In this paper, a modeling methodology is validated based on an enhanced model of the diode, that we have developed to simulate substrate current coupling mechanisms on a typical H -bridge structure. An equivalent schematic based on an enhanced model of the diode was previously proposed to account for minority and majority carrier propagation in the substrate and implemented in Verilog-A code. In this study, the injected parasitic substrate current from high-voltage MOSFETs structure is simulated in a circuit-level simulator and with a finite element method, as well. Both are compared to measurements and confirm a very good agreement up to 400 K. Not only the simulation resources needed by the proposed equivalent schematics are greatly reduced with regard to the finite element approach, but this circuit-level modeling methodology is fully compatible with Spice-like simulations of complex ICs. © 2011 IEEE.

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Type
research article
DOI
10.1109/TPEL.2011.2119495
Web of Science ID

WOS:000296982100007

Author(s)
Conte, Fabrizio Lo  
•
Sallese, Jean-Michel  
•
Kayal, Maher  
Date Issued

2011

Published in
IEEE Transactions on Power Electronics
Volume

26

Issue

10

Start page

2788

End page

2793

Subjects

grated circuit

•

lumped modeling

•

methodology modeling

•

noise

•

parasitic coupling

•

power parasitic modeling

•

power semiconductor devices

•

smart power IC

•

substrate modeling

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
GR-KA  
EDLAB  
Available on Infoscience
November 7, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/72339
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