Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Journal articles
  4. Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages
 
research article

Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages

Zhang, Jian  
•
De Marchi, Michele  
•
Sacchetto, Davide  
Show more
2014
IEEE Transactions on Electron Devices

Gate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon Wnanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V-T). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V-T. This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of similar to 0.5 V between low-V-T and high-V-T configurations, while high-V-T configuration reduces the leakage current by two orders of magnitude as compared to low-V-T configuration.

  • Files
  • Details
  • Metrics
Loading...
Thumbnail Image
Name

06915729.pdf

Access type

openaccess

Size

2.13 MB

Format

Adobe PDF

Checksum (MD5)

1b50087e1cea4cea3dd2684110071621

Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés