conference paper
A 32-Channel 196-μW Logarithmic SoC for Brain Network Connectivity Extraction and Adaptive Psychiatric Symptom Classification
June 8, 2025
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents a 32-channel brain-computer interface SoC for closed-loop deep-brain stimulation in psychiatric disorders. The SoC integrates a 32-channel analog front-end, an efficient logarithmic feature extraction engine, a neural additive model classifier with online update, and a multimode stimulation controller. Fabricated in 65nm CMOS, the 5.46mm² SoC consumes 6.14µW/channel, enabling accurate, low-power, and adaptive detection of psychiatric states.
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C21_4.pdf
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Main Document
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Accepted version
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openaccess
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CC BY
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3.28 MB
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Adobe PDF
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