In this paper, a low-power and high-precision time-domain winner-take-all (WTA) circuit is proposed which is based on a novel group search algorithm. The proposed method, which determines the winner input within a single clock cycle, not only demands no multi-input positive-feedback latch, but also reduces the number of required latches. Therefore, the accuracy of the circuit is improved, and its power consumption is significantly reduced. In order to reduce the power consumption further, power gating and clock gating techniques are utilized for the employed delay lines. Post-layout simulation results for a 4-input WTA circuit in a 65-nm standard CMOS technology with a supply voltage of 0.5 V show that the total power consumption of the proposed structure at the operating frequency of 1 MHz is approximately 60 nW. Moreover, the precision of the circuit is 99.8%, and the silicon area occupied by the circuit is 16μm×34μm.