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  4. 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS
 
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conference paper

10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS

Shokrollahi, Amin  
•
Carnelli, Dario
•
Fox, John
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2016
2016 IEEE International Solid-State Circuits Conference (ISSCC)
2016 IEEE International Solid-State Circuits Conference (ISSCC)

High-speed signaling over package substrates is key to delivering the promise of 2.5D integration. Applications abound and include high-density memory interfaces, sub-division of large dies to increase yield and lower development time, sub-division of a die to achieve upward or downward scalability, or connecting to an off-chip SerDes or optics engine. Each of these in-package applications typically has high throughput and onerously low power constraints along with a low-loss channel. Several solutions have been proposed. Interposer substrates [1], or Chip-on-Substrate-on-Wafer [2] allow for very high-density wiring and low power using CMOS transceivers. Their high manufacturing and testing cost makes them prohibitive for anything but high-end applications. A different approach using high-speed ground-referenced single-ended signaling is reported in [3], which is intended for shorter channels up to 4.5mm and a BER of 1e-12. An approach using differential signaling on up to 0.75" of Megtron 6 material and a BER of 1e-9 is reported in [4]. A comparison is given in Fig. 10.1.1.

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Type
conference paper
DOI
10.1109/ISSCC.2016.7417967
Author(s)
Shokrollahi, Amin  
•
Carnelli, Dario
•
Fox, John
•
Hofstra, Klaas
•
Holden, Brian
•
Hormati, Ali  
•
Hunt, Peter
•
Johnston, Margaret
•
Keay, John
•
Pesenti, Sergio
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Date Issued

2016

Published in
2016 IEEE International Solid-State Circuits Conference (ISSCC)
ISBN of the book

978-1-4673-9467-3

Subjects

algoweb_electronics

•

integrated circuit packaging

•

SerDes technologies

•

Chord signaling

Peer reviewed

REVIEWED

Written at

OTHER

EPFL units
ALGO  
Event nameEvent placeEvent date
2016 IEEE International Solid-State Circuits Conference (ISSCC)

San Francisco, USA

January 31 - Feb 4, 2016

Available on Infoscience
November 23, 2016
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/131598
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