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  4. High Frame-Rate Low-Power Compressive Sampling CMOS Image Sensor Architecture
 
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conference poster not in proceedings

High Frame-Rate Low-Power Compressive Sampling CMOS Image Sensor Architecture

Katic, Nikola  
•
Hosseini Kamal, Mahdad  
•
Kilic, Mustafa  
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2013
23rd Great Lakes Symposium on VLSI

A novel compressive sampling scheme suitable for highly scalable hardware implementation is presented. The prototype design is implemented in a 0.18um standard CMOS technology and utilizes compressed acquisition to achieve high frame rates and maintain low power consumption. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Per column Dierential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the device noise, mismatch and non-linearity, are analyzed and their eects on compressed image acquisition are presented and discussed. The final simulation results show that the proposed 256x256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed architecture can easily be scaled towards newer technology nodes and higher image resolutions.

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Type
conference poster not in proceedings
Author(s)
Katic, Nikola  
•
Hosseini Kamal, Mahdad  
•
Kilic, Mustafa  
•
Schmid, Alexandre  
•
Vandergheynst, Pierre  
•
Leblebici, Yusuf  
Date Issued

2013

Subjects

CMOS Image Sensor

•

Image Acquisition

•

Compressive Sam- pling

•

High Frame Rate

•

Low-Power

•

Cyclic ADC

Written at

EPFL

EPFL units
LSM  
LTS2  
Event nameEvent placeEvent date
23rd Great Lakes Symposium on VLSI

Paris, France

May 2-3, 2013

Available on Infoscience
May 16, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/92267
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