In this paper, a low temperature flip-chip integration technique for Si bare dies is demonstrated on flexible PET substrates with screen-printed circuits. The proposed technique is based on patterned blind vias in dry film photoresist (DP) filled with isotropic conductive adhesive (ICA). The DP material serves to define the vias, to confine the ICA paste (80 mu m-wide and potentially 25 mu m-wide vias), as an adhesion layer to improve the mechanical robustness of the assembly, and to protect additional circuitry on the substrate. The technique is demonstrated using gold-bumped daisy chain chips (DCCs), with electrical vias resistances in the order to hundreds of milliohms, and peel/shear adhesion strengths of 0.7 N mm(-1) and 3.2 MPa, respectively, (i.e. at 1.2 MPa of bonding pressure). Finally, the mechanical robustness to bending forces was optimized through flexural mechanics models by placing the neutral plane at the DCC/DP adhesive interface. The optimization was performed by reducing the Si thickness from 400 to 37 mu m, and resulted in highly robust integrated assemblies withstanding 10 000 cycles of dynamic bending at 40 mm of radius, with relative changes in vias resistance lower than 20%. In addition, the electrical vias resistance and adhesion strengths were compared to samples integrated with anisotropic conductive adhesives (ACAs). Besides the low temperature and high integration resolution, the proposed method is compatible with large area fabrication and multilayer architectures on foil.