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  4. Fast Out-of-order Processor Simulation Using Memoization
 
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conference paper

Fast Out-of-order Processor Simulation Using Memoization

Schnarr, Eric
•
Larus, James R.
1998
Eighth International Conference on Architectural Support for Programming Languages and Operating Systems

Our new out-of-order processor simulatol; FastSim, uses two innovations to speed up simulation 8--15 times (vs. Wisconsin SimpleScalar) with no loss in simulation accuracy. First, FastSim uses speculative direct-execution to accelerate the functional emulation of speculatively executed program code. Second, it uses a variation on memoization---a well-known technique in programming language implementation---to cache microarchitecture states and the resulting simulator actions, and then "fast forwards" the simulation the next time a cached state is reached. Fast-forwarding accelerates simulation by an order of magnitude, while producing exactly the same, cycle-accurate result as conventional simulation.

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Type
conference paper
DOI
10.1145/291069.291063
Author(s)
Schnarr, Eric
•
Larus, James R.
Date Issued

1998

Publisher

ACM

Journal
Eighth International Conference on Architectural Support for Programming Languages and Operating Systems
Start page

283

End page

294

Peer reviewed

REVIEWED

Written at

OTHER

EPFL units
UPLARUS  
Available on Infoscience
December 23, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/98789
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