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conference paper

Global 2D modeling of minority and majority substrate coupled currents

Lo Conte, F.  
•
Sallese, Jean-Michel  
•
Pastre, M.  
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2009
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

This paper presents a modeling strategy to simulate 2D propagation of electrical perturbations induced by direct biasing of substrate junctions. Identifying parasitic substrate devices such as bipolar transistors reaches rapidly its limit when multiple current paths exist as in two-dimensional devices. In this work, we propose to map the substrate using only PN junctions and diffusion resistances. The model of these components has been extended in order to satisfy the majority and minority carrier continuity equation at the boundary of the component. A typical 2D parasitic structure has been simulated and the results are in good agreements with finite element simulation. The proposed approach reduces drastically the time needed to simulate a complex structure such as a whole IC substrate. ©2009 IEEE.

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Type
conference paper
DOI
10.1109/ESSDERC.2009.5331455
Scopus ID

2-s2.0-72849128750

Author(s)
Lo Conte, F.  
•
Sallese, Jean-Michel  
•
Pastre, M.  
•
Krummenacher, F.  
•
Kayal, M.  
Date Issued

2009

Published in
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Start page

153

End page

156

Note

Electronic Laboratory (E-lab.epfl.ch), EPFL, 1015 Lausanne, Switzerland

Export Date: 19 January 2010

Source: Scopus

Art. No.: 5331455

References: Murari, B., Bertotti, F., Vignola, G., (2002) Smart Power ICs, pp. 218-220. , 2nd Edition, pp, Springer-Verlag, Berlin; Schenkel, M., (2003) Substrate Current Effects in Smart Power ICs, , Hartung-Gorre-Verlag, ISBN 3-89649-848-7; Troutman, R.R., Latchup in CMOS Technology The problem and its Cure (1995) Kluwer Academic Publishers second Printing; Widlar, R.J., Controlling substrate currents in junction-isolated ICs (1991) IEEE J. Solid-State Circuits, 26, pp. 1090-1097. , Aug; Gonnard, O., Charitat, G., Lance, P., Stefanov, E., Suquet, M., Bafleur, M., Mauran, N., Peyre-Lavigne, A., Substrate current protection in smart power ICs (2000) Proc. Int. Symp. Power Semiconductor Devices & ICs, pp. 169-172; Horn, W., Zitta, H., A robust smart power bandgap reference circuit f or use in an automotive environment (2002) IEEE Journal of Solid-State, 37 (7), pp. 949-952; V. Venkatesan, Q. Nguyen, A. Bose, P.Panis, DC substrate coupling between LDMOS and CMOS devices in hyper-integration I technology, IEEE BCTM 3.2, pp57-60, 1998Lo Conte, F., Pastre, M., Sallese, J.M., Krummenacher, F., Kayal, M., Substrate Current Modeling for High-Voltage Smart Power BCD Technology (2008) IEEE NEWCAST-TAISA, pp. 141-144; Clement, F.J.R., Zysman, E., Kayal, M., Declercq, M., LAYIN: Toward a global solution for parasitic coupling modeling and visualization (1994) IEEE Custom Integrated Circuits Conference; Birrer, P., Fiez, T.S., Mayaram, K., (2004) Silencer!: A tool for substrate noise coupling analysis, IEEE SOC Conference; Coupling Wave Solutions (CWS), , http.//www.cwseda.com, accessed January 2009; Oehmen, J., Olbrich, M., Hedrich, L., Barke, E., Modeling Lateral Parasitic Transistors in Smart Power ICs, IEEE (2006) Trans. on Device and Materials Reliability, 6 (3), pp. 408-420. , September; Neamen, D.A., (1992) Semiconductor Physics and Devices, , Irwin, Homewood; Sze, S.M., (1981) Physics of Semiconductor Device, , 2nd Edition, Wiley

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REVIEWED

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Available on Infoscience
October 21, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/55923
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