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  4. Compiler Generation for Performance-Oriented Embedded DSLs (Short Paper)
 
conference paper

Compiler Generation for Performance-Oriented Embedded DSLs (Short Paper)

Shaikhha, Amir
•
Jovanovic, Vojin
•
Koch, Christoph E.  
January 1, 2019
Proceedings Of The 18Th Acm Sigplan International Conference On Generative Programming: Concepts And Experiences (Gpce '19)
18th ACM SIGPLAN International Conference on Generative Programming - Concepts and Experiences (GPCE)

In this paper, we present a framework for generating optimizing compilers for performance-oriented embedded DSLs (EDSLs). This framework provides facilities to automatically generate the boilerplate code required for building DSL compilers on top of the existing extensible optimizing compilers. We evaluate the practicality of our framework by demonstrating a real-world use-case successfully built with it.

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Type
conference paper
DOI
10.1145/3357765.3359520
Web of Science ID

WOS:000556729500010

Author(s)
Shaikhha, Amir
Jovanovic, Vojin
Koch, Christoph E.  
Date Issued

2019-01-01

Publisher

ASSOC COMPUTING MACHINERY

Publisher place

New York

Published in
Proceedings Of The 18Th Acm Sigplan International Conference On Generative Programming: Concepts And Experiences (Gpce '19)
ISBN of the book

978-1-4503-6980-0

Start page

94

End page

101

Subjects

domain-specific languages

•

compiler-compiler

•

language embedding

•

language workbench

•

language

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
DATA  
Event nameEvent placeEvent date
18th ACM SIGPLAN International Conference on Generative Programming - Concepts and Experiences (GPCE)

Athens, GREECE

Oct 21-22, 2019

Available on Infoscience
August 21, 2020
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/171012
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