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  4. Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers
 
research article

Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers

Meng, Fanfan
•
Lee, Siang Yun  
•
Zografos, Odysseas
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2025
IEEE Transactions on Circuits and Systems I: Regular Papers

It is envisaged that spintronic logic devices will ultimately be utilized in hybrid CMOS-spintronic systems where signal interconversion between magnetic and electrical domains via transducers takes place. This underscores the vital role of transducers in influencing the overall performance of such hybrid systems. This paper addresses the question: Can spintronic circuits based on Magnetic Tunnel Junction (MTJ) transducers outperform their state-of-the-art CMOS counterparts? To this end, we use the EPFL (École Polytechnique Fédérale de Lausanne) combinational benchmark sets, synthesize them in 7 nm CMOS and in MTJ transducer based spintronic technologies, and compare the two implementation methods in terms of Energy-Delay-Product (EDP). To fully utilize the technologies' potential, CMOS and spintronic implementations are built upon standard Boolean and Majority Gates, respectively. For the spintronic circuits, we assumed that domain conversion (electric/magnetic to magnetic/electric) is performed by means of MTJs and the computation is accomplished by domain wall (DW)-based majority gates, and considered two EDP estimation scenarios: (i) Uniform Benchmarking, which ignores the circuit's internal structure and only includes domain transducers' power and delay contributions into the calculations, and (ii) Majority-Inverter-Graph Benchmarking, which also embeds the circuit structure, the associated critical path delay and energy consumption by DW propagation. Our results indicate that, for the uniform case, the spintronic route is better suited for the implementation of complex circuits with few inputs and outputs. On the other hand, when the circuit structure is also considered via majority and inverter synthesis, our analysis clearly indicates that in order to match and eventually outperform CMOS performance, MTJ transducers' efficiency has to be improved by 3-4 orders of magnitude. While it is clear that for the time being the MTJ-based-spintronic way cannot compete with CMOS, further technological transducer developments may tip the balance, which, when combined with information non-volatility, may make spintronic implementation for certain applications that require a large number of calculations and have a rather limited amount of interaction with the environment.

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Type
research article
DOI
10.1109/TCSI.2024.3420250
Scopus ID

2-s2.0-85215558070

Author(s)
Meng, Fanfan

Departement Elektrotechniek (ESAT)

Lee, Siang Yun  

École Polytechnique Fédérale de Lausanne

Zografos, Odysseas

Interuniversity Microelectronics Centre

Gupta, Mohit

Interuniversity Microelectronics Centre

Nguyen, Van D.

Interuniversity Microelectronics Centre

Micheli, Giovanni De  

École Polytechnique Fédérale de Lausanne

Cotofana, Sorin

Delft University of Technology

Asselberghs, Inge

Interuniversity Microelectronics Centre

Adelmann, Christoph

Interuniversity Microelectronics Centre

Kar, Gouri Sankar

Interuniversity Microelectronics Centre

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Date Issued

2025

Published in
IEEE Transactions on Circuits and Systems I: Regular Papers
Volume

72

Issue

1

Start page

135

End page

142

Subjects

domain wall devices

•

Magnetic logic

•

magnetic tunnel junction

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSI1  
Available on Infoscience
January 30, 2025
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/246033
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