This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricate 4-layer CMOS memory chip stacks, which were then packaged and tested using time domain reflectometry (TDR) measurement technique. The results have showed that the characteristic inductance values were improved for 3D integrated memory chips due to the elimination of bonding wires.