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  4. Associativity-agnostic in-cache computing memory architecture optimized for multiplication
 
patent

Associativity-agnostic in-cache computing memory architecture optimized for multiplication

Rios, Marco Antonio  
•
Simon, Wiliiam Andrew
•
Levisse, Alexandre Sébastien  
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2021

A random access memory array including a plurality of local memory group ways, each local memory group way including, a plurality of local memory groups, each local memory group including, a memory column including a plurality of memory cells, a pair of local bitlines operatively connected to the plurality of memory cells, and a local group periphery including a local bitline multiplexer operatively connected with the pairs of local bitlines of the corresponding local memory group; and a pair of global read bitlines operatively connected to outputs of the plurality of local group peripheries, a global read bitline multiplexer operatively connected to outputs of the plurality of pairs of the global read bitlines from the local memory group ways, and a bitline operational block operatively connected an output of the global read bitline multiplexer.

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Type
patent
EPO Family ID

78413131

Author(s)
Rios, Marco Antonio  
Simon, Wiliiam Andrew
Levisse, Alexandre Sébastien  
Zapater, Marina  
Atienza Alonso, David  
Subjects

TO 6.2092

EPFL units
AVP-R-TTO  
ESL  
IdentifierCountry codeKind codeDate issued

US11211115

US

B2

2021-12-28

US2021350846

US

A1

2021-11-11

Available on Infoscience
December 3, 2021
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/183463
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