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research article

Capacitorless 1T DRAM sensing scheme with automatic reference generation

Blagojevic, M.
•
Kayal, M.  
•
Pastre, M.  
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2006
Ieee Journal of Solid-State Circuits

To perform a current sensing in capacitorless 1-transistor (IT) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state "1" the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-mu m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1 s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 us.

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Type
research article
DOI
10.1109/jssc.2006.874357
Web of Science ID

WOS:000238153800023

Author(s)
Blagojevic, M.
•
Kayal, M.  
•
Pastre, M.  
•
Harik, L.
•
Declercq, M. J.
•
Okhonin, S.
•
Fazan, P. C.
Date Issued

2006

Published in
Ieee Journal of Solid-State Circuits
Volume

41

Issue

6

Start page

1463

End page

1470

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ELAB  
LEG1  
Available on Infoscience
October 21, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/55889
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