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  4. Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware
 
conference paper

Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware

Burdina, Anna  
•
Catel Torres, Gabriel
•
Schiavone, Davide  
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August 5, 2024
Proceedings of the 29th International Symposium on Low Power Electronics and Design, ISLPED 2024
29 ACM/IEEE International Symposium on Low Power Electronics and Design

In the past decade, computing systems have significantly increased in complexity and power consumption. Nowadays, heterogeneous multi-processor systems-on-chip (MPSoCs) integrate many computing cores. Heterogeneous MPSoCs often comprise general-purpose processors and a variety of accelerators, thus supporting specialized functions for the target application domain to minimize overall energy when executing a specific task. The ensuing architectural design space is, therefore, increasingly multi-dimensional, especially in the light of upcoming 2.5D/3D chiplets integration, which, on one side, allows unprecedented system integration possibilities but, on the other, exacerbates data transfer bottlenecks and affects overall power consumption significantly. To traverse such space in search of high-performance/high-efficiency solutions, we introduce a cross-layer approach combining fast explorations with virtual systems with modular open-hardware design frameworks. This paper showcases how these two approaches effectively cross-fertilize: detailed hardware designs are essential in calibrating performance, power and temperature models, and validating simulation outcomes. Conversely, full system simulation is crucial for projecting the impact of design choices towards complex but energy-efficient heterogeneous multi-processor architectures.

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Type
conference paper
DOI
10.1145/3665314.3680474
Scopus ID

2-s2.0-85204969014

Author(s)
Burdina, Anna  

École Polytechnique Fédérale de Lausanne

Catel Torres, Gabriel

University of Applied Sciences Western Switzerland

Schiavone, Davide  

École Polytechnique Fédérale de Lausanne

Peón-Quirós, Miguel  

École Polytechnique Fédérale de Lausanne

Ansaloni, Giovanni  

École Polytechnique Fédérale de Lausanne

Atienza, David  

École Polytechnique Fédérale de Lausanne

Zapater, Marina

University of Applied Sciences Western Switzerland

Date Issued

2024-08-05

Publisher

Association for Computing Machinery, Inc

Published in
Proceedings of the 29th International Symposium on Low Power Electronics and Design, ISLPED 2024
ISBN of the book

9798400706882

Subjects

chiplets

•

heterogeneous chiplets integration

•

multiprocessor system-on-chip

•

open hardware

•

simulation

•

system integration

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
ESL  
ECOCLOUD-GE  
Event nameEvent acronymEvent placeEvent date
29 ACM/IEEE International Symposium on Low Power Electronics and Design

Newport Beach, United States

2024-08-05 - 2024-08-07

Available on Infoscience
January 26, 2025
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/245016
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