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  4. Gate-All-Around Buckled Dual Si Nanowire nMOSFETs on Bulk Si for Transport Enhancement and Digital Logic Application
 
conference paper not in proceedings

Gate-All-Around Buckled Dual Si Nanowire nMOSFETs on Bulk Si for Transport Enhancement and Digital Logic Application

Najmzadeh, Mohammad  
•
Tsuchiya, Yoshishige
•
Bouvet, Didier  
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2012
38th International Conference on Micro and Nano Engineering (MNE)
  • Details
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Type
conference paper not in proceedings
Author(s)
Najmzadeh, Mohammad  
Tsuchiya, Yoshishige
Bouvet, Didier  
Grabinski, Wladyslaw  
Ionescu, Mihai Adrian  
Date Issued

2012

Subjects

Gate-all-around Si nanowire MOSFET

•

Uniaxial tensile stress

•

Vertical stack of nanowires

•

Micro-Raman spectroscopy

•

Optical/electrical characterization methods in nanoscale

•

Inversion-mode

•

Mutli-gate logic on bulk Si

URL

URL

http://www.mne12.org/en/?page_id=964
Editorial or Peer reviewed

NON-REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Event nameEvent placeEvent date
38th International Conference on Micro and Nano Engineering (MNE)

Toulouse, France

September 16-20, 2012

Available on Infoscience
July 10, 2012
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/83722
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