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  4. Design of Low-power Analog Circuits in Advanced Technology Nodes using the Gm/ID Approach
 
conference paper

Design of Low-power Analog Circuits in Advanced Technology Nodes using the Gm/ID Approach

Enz, Christian  
•
Han, Hung-chi  
•
Berner, Simon  
January 1, 2023
2023 Ieee International Symposium On Circuits And Systems, Iscas
56th IEEE International Symposium on Circuits and Systems (ISCAS)

The Gm/ID approach has proven to be an efficient technique for the design of low-power analog circuits. Until now it was mostly demonstrated on older CMOS technology nodes. In this paper we will show that the Gm/ID methodology still holds for advanced technologies using the simplified EKV model which only requires 4 parameters for bulk and 5 for FDSOI. We will start with a brief presentation of the simplified EKV model highlighting how the normalization process can strip- off most of the technology dependence. Then we will introduce the concept of inversion coefficient IC and show that the normalized Gm/ID only depends on IC and a parameter λc accounting for velocity saturation. Then we will show how to extract the few parameters needed from data either generated from the PDK or from measurements. We then will illustrate the methodology by a design example of an OTA in a 22nm FDSOI technology. The design is then validated by simulations using the founder PDK using the full BSIM-IMG compact model demonstrating an excellent agreement between the simulation results and the specifications despite the simplicity of the model and the methodology.

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Type
conference paper
DOI
10.1109/ISCAS46773.2023.10181364
Web of Science ID

WOS:001038214600025

Author(s)
Enz, Christian  
Han, Hung-chi  
Berner, Simon  
Date Issued

2023-01-01

Publisher

IEEE

Publisher place

New York

Published in
2023 Ieee International Symposium On Circuits And Systems, Iscas
ISBN of the book

978-1-6654-5109-3

Series title/Series vol.

IEEE International Symposium on Circuits and Systems

Subjects

Computer Science, Artificial Intelligence

•

Computer Science, Information Systems

•

Engineering, Electrical & Electronic

•

Computer Science

•

Engineering

•

voltage

•

methodology

•

model

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

Event nameEvent placeEvent date
56th IEEE International Symposium on Circuits and Systems (ISCAS)

Monterey, CA

May 21-25, 2023

Available on Infoscience
September 11, 2023
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/200417
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